1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that can prevent the latch-up phenomenon from happening.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 shows a simplified diagram of a conventional semiconductor device 100. As shown in FIG. 1, the semiconductor device 100 comprises: a P type semiconductor substrate 102, an N-well 104, a first P+ diffusion region 106, a first N+ diffusion region 108, a second N+ diffusion region 110, a second P+ diffusion region 112, a third P+ diffusion region 114, a first insulation layer 116, a second insulation layer 118, a first parasitic bipolar junction transistor (BJT) 120, and a second parasitic BJT 122. The N-well 104 is positioned in the P type semiconductor substrate 102. The first P+ diffusion region 106 is positioned in the N-well 104. The first P+ diffusion region 106 is coupled to an input signal VDD1. The first N+ diffusion region 108 and the second N+ diffusion region 110 are positioned in the N-well 104, and utilized for coupled to a voltage source VDD2, respectively. The second P+ diffusion region 112 and the third P+ diffusion region 114 are positioned in the P type semiconductor substrate 102, and utilized for coupled to a voltage level VSS1, respectively. The first insulation layer 116 is positioned between the first N+ diffusion region 108 and the second P+ diffusion region 112. The second insulation layer 118 is positioned between the second N+ diffusion region 110 and the third P+ diffusion region 114. The first parasitic BJT 120 has an emitter, a base, and a collector, wherein the emitter of the first parasitic BJT 120 is formed by the first P+ diffusion region 106, the base of the first parasitic BJT 120 is formed by the N-well 104 connected to the first N+ diffusion region 108, and the collector of the first parasitic BJT 120 is formed by the P type semiconductor substrate 102 connected to the second P+ diffusion region 112. The second parasitic BJT 122 has an emitter, a base, and a collector, wherein the emitter of the second parasitic BJT 122 is formed by the first P+ diffusion region 106, the base of the second parasitic BJT 122 is formed by the N-well 104 connected to the second N+ diffusion region 110, and the collector of the second parasitic BJT 122 is formed by the P type semiconductor substrate 102 connected to the third P+ diffusion region 114.
Please refer to FIG. 2. FIG. 2 shows a timing diagram of the voltage level VSS1, the input signal VDD1, and the voltage source VDD2 in FIG. 1. As shown in FIG. 2, the voltage level lifting speed of the input signal VDD1 is faster than the voltage level lifting speed of the voltage source VDD2, and thus when the voltage level of the input signal VDD1 is higher than the voltage level of the voltage source VDD2, the first parasitic BJT 120 and the second parasitic BJT 122 will be conducted, and a latch-up phenomenon will appear. In this way, a large current will be generated to damage the semiconductor device 100 easily.